Samsung SC32442

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Структурная схема микропроцессора
Структурная схема микропроцессора

SC32442 MSP product is a proprietary solution provided exclusively by Samsung Electronics. SC32442 includes an S3C2442 AP(Application Processor) and a memory MCP (Multiple Chip Package). SC32442 is a best fit solution for smart phones, wireless PDAs, and other mobile handheld devices, providing them and their general applications with a cost-effective, low-power, and high-performance solution all incorporated in one tiny MSP. This allows companies to fully utilize the form-factor of their products via a smaller footprint on the PCB (Printed Circuit Board). S3C2442 AP features an ARM920T core, a 16/32-bit RISC microprocessor, to provide the general applications of smart phones/hand-held devices with low-power and a high-performance micro-controller solution. S3C2442 is developed using 0.13um CMOS standard cells and a memory compiler. Especially, the S3C2442's power consumption was dramatically reduced by using an MTCMOS library. By providing a comprehensive set of common system peripherals, the S3C2442 saves overall system cost and eliminates the need to configure additional components. S3C2442 includes the following components: separate 16 KB instruction cache and 16 KB data cache, MMU to handle virtual memory management, TFT and STN LCD controller, NAND flash boot loader, system manager (chip select logic and SDRAM controller), 3-ch UART, 4-ch DMA, 4-ch timers with PWM, I/O ports, RTC, 8-ch 10-bit ADC and touch screen interface, camera interface, IIC-BUS interface, IIS-BUS interface, USB host, USB device, SD host and multimedia card interface, 2-ch SPI and PLL for clock generation.

Особенности

  1. ARM920T CPU Core
    • 64-way set-associative cache with :
    • I-Cache (16 KB) and D-Cache (16 KB)
    • Write-through and Write-back cacheoperation.
    • MMU supports WinCE and LINUX.
    • Internal AMBA bus architecture (AMBA2.0, AHB/APB)
  2. Stacked Memory Configuration
    • MCP1 : 256Mb mSDRAM (x32) + 512Mb NAND (x8)
    • MCP2 : 256Mb mSDRAM (x32) + 1Gb NAND (x8)
    • MCP3 : 512Mb mSDRAM (x32) + 1Gb NAND (x8)
    • MCP4 : 512Mb mSDRAM (x32) + 2Gb NAND (x8)
    • MCP5 : 512Mb mSDRAM (x32)
  3. System Manager
    • Little/Big-Endian support
    • Address space : 128MB for each bank (total 1GB)
    • 8 memory banks :
      • 6 memory banks for ROM, SRAM, and others
      • 2 memory banks for ROM/SRAM/SDRAM
    • NAND Flash Boot Loader
      • 4 KB internal buffer for booting
      • Supports storage memory after booting
    • Power Manager : supports STOP/SLEEP/IDLE mode
  4. On-chip Peripherals
    • NAND Flash Controller (Normal/Advanced)
    • LCD Controller (up to 4K color STN and 256K color TFT) with 1-ch LCD dedicated to DMA
    • Camera Interface supporting up to 4096 x 4096 resolution (2048 x 2048 pixel input support for scaling)
    • USB Host/Device Interface
      • 2 ports USB Host (Version 1.1 Compliant)
      • 1 port USB Device (Version 1.1 Compliant)
    • 4-ch DMA Controllers
    • 3-ch UARTs with IrDA 1.0 (Including 64 byte FIFO)
    • 1-ch multi-master I2C-Bus Interface
    • 1-ch I2S-Bus Interface
    • 4-ch 16 bit PWMs (Pulse Width Modulation) and 1-ch 16-bit timer for OS
    • 130 multiplexed GPIO ports
    • 8-ch 10-bit ADCs (Max. 500KSPS), including TSP Controller
    • 16-bit Watch-dog Timer
    • RTC with calendar function
    • On-chip clock generator with PLL
    • 2-ch SPIs (Synchronous Serial I/O)
    • SD Host/MMC (Multimedia Card) Interface
    • Debug and TEST
  5. Operating Conditions
    • Internal : 1.35/1.5V
    • External I/O : 2.3~3.6V
    • Speed : 300MHz @1.35V
      400MHz @1.5V
    • Memory : 1.8V
  6. Package 332 FBGA 14 X 14

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